Due to the needs for portability and multi-functionality of the consumer electronics, the semiconductor devices are developed to exhibit a smaller size, a higher performance, and a lower cost. With the advantage of being a small-sized package, wafer-level packages (WLP) meet the market trend of electronic products. Among the WLP techniques, the fan-out panel level package (FO-PLP) carrying a chip with a large-sized plate substrate and adopting a redistribution layer is able to facilitate the yield. Thus, FO-PLP has become one of the promising techniques.
Currently, FO-PLP may adopt two types of fabricating processes. In one of the types, the redistribution layer is fabricated after the chip is encapsulated by a molding compound material. In the other type, the redistribution layer is fabricated, the chip is electrically connected to the redistribution layer, and then, the molding compound is formed. In these types of fabricating processes, the issues of non-planarity, alignment precision, and warpage may easily occur in the large-sized plate substrate, the difference in thermal expansion coefficient as well as the difference in internal stress between the layers and between the layers and the chips during the molding process. Accordingly, how to reduce the non-planarity and warpage and facilitate the alignment precision have become the issues for people skilled in the art to work on.